1. Field of Invention
The present invention relates to a memory device testing apparatus. In particular, the present invention relates to a memory device testing apparatus for testing a packet system memory device.
2. Description of Related Art
FIG. 1 shows a schematic view of a conventional memory device testing apparatus for testing a memory device. This memory device testing apparatus has a pattern generator 10, a pin data selector 20, a waveform shaper 30, a memory device socket 40, and a comparator 50. A memory device 45 is held into a socket 42 on the memory device socket 40 during the test. The pattern generator 10 generates a pattern signal 12, which contains an address, a control signal 25, and data to be provided to the memory device 45. The data contains an expectation value data signal 27, which is compared with output a signal 44 output from the memory device 45 by the comparator 50. The pattern signal 12 generated from the pattern generator 10 is sent to the pin data selector 20.
A test data signal 26 is to be written into the memory device 45 according to the address and the control signal 25 provided to the memory device 45. The expectation value data signal 27 is the expectation value which is expected to output from memory device 45 if the memory device 45 is normal. The expectation value data signal 27 is compared with the output signal 44 read from the memory device socket 40 by comparator 50.
The pin data selector 20 selects the address and the control signal 25, which is part of the pattern signal 12, to allocate the address and the control signal 25 to corresponding pins on the memory device socket 40. The Pin data selector 20 outputs the test data signal 26, which is written into the memory device 45, and the expectation value data signal 27, which is compared with the output signal 44 output from the memory device 45, by the comparator 50. The test data signal 26 and the expectation value data signal 27 have the same signal pattern.
The address and the control signal 25 generated from the pin data selector 20 are sent to the waveform shaper 30. The waveform shaper 30 shapes the waveform of the address and the control signal 25 to adjust the waveform of the address and the control signal 25 to the characteristic of the memory device 45, and the waveform shaper 30 outputs the waveform-shaped address and control signal 32. The waveform shaper 30 also adjusts the timing for providing the signal to the memory device 45. The waveform-shaped address and control signal 32 are provided to the memory device socket 40.
When the control signal 25 means write request, which requests the data to be written, the waveform of the test data signal 26 is shaped by the waveform shaper 30, and the resulting waveform-shaped test data signal 33 is written into the memory device 45. The test data, which is written into the memory device 45, is output from the memory device socket 40 in response to a read request signal generated from the pattern generator 10. The output signal 44 is input to the comparator 50 to be compared with the expectation value data signal 27.
FIG. 2 shows a block diagram of a sub pin data selector 20a in the pin data selector 20. The pin data selector 20 has the same number of sub pin data selectors 20a as the number of signal input pins of the memory device 45. The sub pin data selector 20a has multiplexers 21a and 23a and registers 22a and 24a. The registers 22a and 24a are respectively connected to the control inputs of the multiplexers 21a and 23a. 
The pattern signal 12 generated from the pattern generator 10 is input to the multiplexer 21a. The multiplexer 21a is controlled by the register 22a. The register 22a indicates which signal should be selected from the pattern signal 12 to the multiplexer 21a. Then, the multiplexer 21a selects one of the addresses signals and one of the control signals 25a to be provided to a specific pin of the memory device 45.
Here, multiplexer 23a and register 24a are not used. Each of the addresses and control signals 25a selected from each sub pin data selector 20a is sent to the waveform shaper 30. The selected addresses and control signals 25a generate one combined address and control signal 25 as a whole. Address and control signal 25 is sent through the waveform shaper 30 to the memory device socket 40 to the memory device 45.
The test data 26 and the expectation value data signal 27 are also output from the sub pin data selector 20a. 
When the test data 26 is supplied to the sub pin data selector 20a, the register 22a indicates which test data signal should be selected from the pattern signal 12 to the multiplexer 21a. Then, the multiplexer 21a selects a test data signal 26a from the pattern signal 12. The waveform of the test data signal 26a is shaped by the waveform shaper 30, and the resulting waveform-shaped test data signal 33a is written into the memory device 45.
The pattern generator 10 provides a read signal to the memory device 45, and the memory device 45 outputs written test data as the output signal 44 to the comparator 50. At that time, the pin data selector 20 outputs the expectation value data signal 27 to the comparator 50. The sub pin data selector 20a selects the expectation value data signal 27a by using the multiplexer 23a and the register 24a in the same way as when the sub pin data selector 20a selects the test data signal 26a. The comparator 50 compares the output signal 44 with the expectation value data signal 27.
As the technology of memory devices has developed, the packet system memory device has come into use, and it is difficult to test packet system memory devices with the conventional memory test apparatus. A packet system memory device is a memory which inputs a plurality of command signals in a packet and writes data sequentially to sequential addresses at high speed. It is important to discover how to generate a test data pattern for testing packet system memory devices.
FIG. 3 shows the pin components of a packet system memory device. This packet system memory device has 10 input pins CA0-CA9 to input address signals and control signals, a clock pin CLK, and 18 data input and output pins DQ0-DQ17. These data input and output pins are divided into 2 sets, DQ0-DQ8 and DQ9-DQ17, and each set inputs and outputs 8 bits of data and 1 parity bit.
FIG. 4 shows an example of a read-write request packet, which is the command signal to be input to the packet system memory device. In this example, a command codes, Cmd5-Cmd0, bank addresses, BNK2-BNK0, row addresses, Row9-Row0, and column addresses, Col6-Col0, are input to the memory device from 10 pins CA0-CA9 over 4 cycles of the clock CLK.
FIG. 5 shows the allocation of tester resources, which corresponds to the read-write request packet shown in FIG. 4. As shown in FIG. 5, multiple signals are allocated to a single pin to input the command signal to the packet system memory device. In this example, 4 signals, C5, X8, 0, and Y0 are allocated to pin CA0. However, the pin data selector 20 of the conventional memory test device can allocate only one signal to a pin. And, the packet signals for each cycle must be generated from the pattern generator 10 to test the packet system memory device with the conventional memory test apparatus.
But it is difficult to generate a packet of signals, which is a block of sequential signals comprising address signals and control signals, by dividing the packet of signals one cycle by one cycle. Especially, as the capacity of memory device become larger, it becomes more difficult to generate the data pattern. In this case, the cost of generating the data pattern increases, so that with the cost of testing memory devices by the conventional memory test apparatus is higher than the market will bear.
Given these problems, it is an object of the present invention to provide a memory device test apparatus, which facilitates the generation of test patterns for packet system memory devices. Also, it is an object of the present invention to provide a circuit which can easily select one output signal from a plurality of signals.
Therefore, it is an object of the present invention to provide a memory device testing apparatus and a data selection circuit which are capable of solving the problems described above. The object of the present invention can be achieved by the combinations of features described in the independent claims of the present invention. The dependent claims of the present invention define further advantageous embodiments of the present invention
The present invention provides a memory device testing apparatus to test a packet system memory device in which input and output data are controlled by plurality of packet signals that contains at least part of an address signal and part of a control signal.
According to the first aspect of the present invention, a memory device testing apparatus for testing a packet system memory device, which is controlled by plurality cycles of a packet signal that contains at least part of an address signal, part of a control signal, part of a test data, and part of an expectation value data that is expected to output from a normal memory device is provided. This memory device testing apparatus has a pattern generator that generates base signals to be used in the plurality cycles of the packet signal in one cycle, a pin data selector that generates each cycle of the packet signal by selecting different signals in each of the plurality cycles from the base signals generated by the pattern generator, and outputting the selected base signals in each of the plurality cycles, a memory device socket which holds the memory device, writes the test data into the memory device, and reads the test data from the memory device by providing each cycle of the packet signal generated by the pin data selector to the memory device, and a comparator that compares the expectation value data generated by the pin data selector with the test data read out from the memory device.
A memory device testing apparatus can be provided such that the pin data selector has a sub pin data selector, which selects an output signal, which constitutes the packet signal, from the base signals in the each cycles and outputs the selected output signal in the each cycles, and a number of the sub pin data selector being larger than a number of signal input pins of the memory device.
A memory device testing apparatus can be provided such that each of the sub pin data selector has a first multiplexer that selects the output signal from the base signals.
A memory device testing apparatus can be provided such that each of the sub pin data selectors has a plurality of registers, which contains a selection data that indicates which the output signal is to be selected from the base signals, and each of the sub pin data selectors selects the output signal according to the selection data.
A memory device testing apparatus can be provide such that each of the sub pin data selectors has a second multiplexer that selects a register from the plurality of registers to output the selection data contained in the selected register, and the first multiplexer selects the output signal according to the selection data output from the second multiplexer.
A memory device testing apparatus can be provided which further has a register selection signal generator which generates a register selection signal to indicate which of a register is to be selected, and the second multiplexer selects the register according to the register selection signal.
A memory device testing apparatus can be provided such that the pattern generator has the register selection signal generator.
A memory device testing apparatus can be provided which further has a waveform shaper that shapes a waveform of the packet signal output from the pin data selector into a type of waveform required by the memory device.
A memory device testing apparatus can be provided such that the contents of the plurality of registers and the register selection signal are programmable according to a type of the memory device.
A memory device testing apparatus can be provided which further has a data selection signal generator which generates a data selection signal that indicates which output signal is to be selected from the base signals, wherein each of the sub pin data selectors has a logic circuit, which inputs some of the base signals and selects the output signal from input base signals in each of the plurality cycles and outputs the output signal in each of the plurality cycles according to the data selection signal.
A memory device testing apparatus can be provided such that the pin data selector has a selector signal selection circuit, which provides each of the output signal output from each of the sub pin data selector to the memory device socket.
A memory device testing apparatus can be provided such that the logic circuit is a programmable logic circuit, and contents of the logic circuit and the data selection signal are programmable according to a type of the memory device.
According to still other aspect of the present invention, a memory device testing apparatus for testing a memory device is provided. The memory device testing apparatus has a pattern generator that generates data signals to be used in a test data which is to be provided to the memory device, a pin data selector that generates the test data and a expectation value data, which is expected to output from a normal memory device, by selecting some of the data signals generated by the pattern generator and outputting the selected data signals plurality times, a memory device socket which holds the memory device, writes the test data into the memory device, and reads the test data from the memory device, and a comparator that compares the expectation value data generated by the pin data selector with the test data read out from the memory device.
A memory device testing apparatus can be provided such that the pin data selector has a sub pin data selector which selects the test data and the expectation value data from the data signals and outputs the test data and the expectation value data plurality times, and a number of the sub pin data selector being larger than a number of signal input pins of the memory device, and each of the sub pin data selectors has a test data selection circuit which selects the test data from the data signals.
A memory device testing apparatus can be provided such that the test data selection circuit has a first multiplexer that selects the test data from the data signals.
A memory device testing apparatus can be provided such that the test data selection circuit has a plurality of registers, which contains a selection data that indicates which the test data is to be selected from the data signals, and the test data selection circuit selects the test data according to the selection data contained in the plurality of registers.
A memory device testing apparatus can be provided such that the test data selection circuit has a second multiplexer that selects a register from the plurality of registers to output the selection data contained in the selected register, and the first multiplexer selects the test data according to the selection data output from the second multiplexer.
A memory device testing apparatus can be provided which further has a waveform shaper that shapes a waveform of the test data generated by the pin data selector into a type of waveform required by the memory device.
A memory device testing apparatus can be provided which further has a data selection signal generator which generates a data selection signal that indicates which the test data is to be selected from the data signals generated by the pattern generator, wherein each of the test data selection circuits has a logic circuit, which inputs some of the data signals generated by the pattern generator and selects the test data from the input data signals and outputs the test data according to the data selection signal.
A memory device testing apparatus can be provided such that the pin data selector has a selector signal selection circuit, which provides each of the test data output from each of the test data selection circuit to the memory device socket.
A memory device testing apparatus can be provided such that each of the sub pin data selectors further has an expectation value data selection circuit to select the expectation value data from the data signals and output the expectation value data to the comparator.
A memory device testing apparatus can be provided such that the expectation value data selection circuit has a first multiplexer that selects the expectation value data from the data signals.
A memory device testing apparatus can be provided such that the expectation value data selection circuit has a plurality of registers, which contains a selection data that indicates which the expectation value data is to be selected from the data signals, and the expectation value data selection circuit selects the expectation value data according to the selection data contained in the plurality of registers.
A memory device testing apparatus can be provided such that each of the expectation value data selection circuits has a second multiplexer that selects a register from the plurality of registers to output the selection data contained in the selected register, and the first multiplexer selects the expectation value data according to the selection data output from the second multiplexer.
A memory device testing apparatus can be provided which further has a register selection signal generator which generates a register selection signal to indicate which of the register is to be selected, and the second multiplexer selects the register according to the register selection signal.
A memory device testing apparatus can be provided which further has a data selection signal generator which generates a data selection signal that indicates which the expectation value data is to be selected from the data signals generated by the pattern generator, wherein each of the expectation value data selection circuits has a logic circuit, which inputs some of the data signals generated by the pattern generator and selects the expectation value data from the data signals and outputs the expectation value data to the comparator according to the data selection signal.
A memory device testing apparatus can be provided such that the pin data selector has a selector signal selection circuit, which provides each of the expectation value data output from each of the expectation value data selection circuit to the memory device socket.
According to still other aspect of the present invention, a data selection circuit, which selects an output signal from plurality signals and outputs the output signal, is provided. The data selection circuit has a first multiplexer in which the plurality signals are input, a plurality of registers, which contains a selection data that indicates which the output signal is to be selected, a second multiplexer that selects a register from the plurality of registers to output the selection data contained in the selected register, and the first multiplexer selects the output signal according to the selection data output from the second multiplexer.
According to still other aspect of the present invention, a data selection circuit, which selects an output signal from plurality signals and outputs the output signal, is provided. The data selection circuit has a logic circuit, which inputs some of the plurality signals and selects the output signal from the input signals and outputs the selected output signal according to a data selection signal that indicates which the output signal is to be selected from the input signals.